1. Field of the Invention
The present invention relates to data processing systems, and more specifically to a method and apparatus for observing the contents cf a central processing unit's internal memory-mapped registers.
2. Discussion of the Prior Art
In conventional digital data processing system with n-bit architecture, the central processing unit (CPU) is capable of generating 2.sup.n addresses for referencing instructions or data. For example, a 16-bit computer is capable of generating 2.sup.16 or 65,536 addresses. These addresses are generally used to reference devices which are located outside the CPU environment, so-called peripheral or external devices. The interface between the CPU and the peripheral devices consists of a system bus, including an address bus and a data bus, wherein the CPU, responding to an instruction request, sends an address onto the address bus which is connected to the peripheral device. If the peripheral device is memory storage, then data can be transferred directly between the CPU and memory by means of the data bus. If, however, the peripheral device is something other than a memory device, such as a printer, modem, or a co-processor, then additional hardware is generally required in the peripheral device in order to decode and act on the address reference.
In order to avoid the need for this additional hardware, a technique called "memory-mapped I/O" is used. According to this technique, the transfer of data to and from peripheral devices is accomplished by using some of the normally available memory space. Memory addresses are decoded within the peripheral device and thus are used to determine when a specific device is being addressed. Usually, each type of function within the peripheral device is assigned a memory address and may then be accessed by the CPU. For example, the status, control and data registers within the peripheral devices are each assigned a memory address and thus three addresses are required for the CPU to perform an I/O operation with this peripheral device. Using memory-mapped I/O in this fashion allows I/O operations to be performed directly in a high-level language, i.e., an I/O device may be declared as a data structure and then manipulated with the use of pointers.
Referring to FIG. 1, in a conventional microprocessor architecture, the sequence of events occurring during a basic CPU access to either memory or peripheral device for a read transaction or a write transaction is performed in two cycles of a bus clock, the cycles commonly being labeled T1 and T2. During the first half of cycle T1, the CPU asserts an Address Strobe signal ADS which indicates that a bus cycle has begun and that a valid address is on the Address Bus. From the beginning of cycle T1 until the completion of the bus cycle, the CPU drives the Address Bus and other relevant control signals. If the bus cycle is not cancelled (e.g. cycle T2 is entered in the next clock cycle), the CPU will assert a Confirm signal CONF in the middle of cycle T1 to indicate that the bus cycle initiated by the Address Strobe ADS is valid. A confirmed bus cycle is completed at the end of cycle T2. In the case of a read operation, the CPU samples the Data Bus at the end of cycle T2. If a bus exception is detected, then data on the Data Bus is ignored. For write operations, valid data is output on the Data Bus to the address indicated on the Address Bus from the middle of cycle T1 until the end of the cycle.
The desire for improved microprocessor performance is leading to integration of certain functions which, in the past, had been external to the CPU (e.g. peripheral devices such as controllers and co-processors). Integration of these functions means that the status, control and data registers associated with the newly-integrated functions are located internally to the CPU, not externally as before. Thus, while these registers may still be referenced as memory-mapped, the CPU access to the internal memory-mapped registers no longer occurs over the external bus, but rather occurs over an internal bus, thus making the transaction essentially transparent to the user. The inability to observe the read/write operations of these internal registers makes it extremely difficult to trace CPU activity and it becomes very difficult to debug the system.
Some systems, e.g., the Intel 80186 microprocessor, solve the problem by showing accesses to internal memory-mapped registers as normal read/write cycles, as described above. However, the CPU ignores the synchronous and asynchronous ready bits as well as the data bus, thus the data contained in the internal memory-mapped registers can not be observed.
In National Semiconductor's HPC 16083 controller, the read and write strobes are inhibited. Thus, during a write operation, the data is presented on the bus, whereas during a read operation, data is not presented on the bus.